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XRS10L620
PCI-X to 2-SATA/1-PATA Host Controller
DATA SHEET
XRS10L620
Rev 1.00
Index
1. XRS10L620 REVISION HISTORY........................................................................................... 2 2. OVERVIEW ................................................................................................................................. 2 3. FEATURES .................................................................................................................................. 3 3-1 General................................................................................................................................. 3 3-2 PCI-X Interface.................................................................................................................... 3 3-3 SATA Interface..................................................................................................................... 3 3-4 IDE Interface ....................................................................................................................... 3 4. BLOCK DIAGRAM .................................................................................................................... 4 5. PIN DIAGRAM............................................................................................................................ 5 5.1 XRS10L620 128-pin Diagram ............................................................................................. 5 5.2 XRS10L620 Pin Assignment ............................................................................................... 6 5.3 Pin Descriptions ................................................................................................................... 7 6. REGISTER DEFINITION.........................................................................................................11 6.1 PCI Configuration Memory Registers : ............................................................................. 11 6.1.1 PCI Power Management Registers : ....................................................................... 12 6.2 PCI-X Capabilities List Item : ........................................................................................... 13 6.2.1 CFGM+4Ch(R) : 32 bits PCI-X Status Register..................................................... 13 6.3 Host Registers definition:................................................................................................... 14 6.3.1 Global host registers : (IOG + 00h to 0FFh)........................................................... 15 6.3.2 Port Registers (length 80h bytes per port/channel):................................................ 22 7. SYSTEM MEMORY STRUCTURE........................................................................................ 41 7.1 Received FIS structure ....................................................................................................... 41 7.2 Command List Structure .................................................................................................... 42 7.3 Command Table and PRD table......................................................................................... 42 8. PCB HIGH-SPEED LAYOUT DESIGN GUIDELINES ....................................................... 43 9. ELECTRICAL CHARACTERISTICS ................................................................................... 44 9.1 Absolute Maximum Ratings............................................................................................... 44 9.2 Typical Operating Condition.............................................................................................. 44 9.3 DC Specifications .............................................................................................................. 45 10. PACKAGE DIMENSION ....................................................................................................... 46 11. APPENDIX ............................................................................................................................... 47 11.1Product ordering information............................................................................................ 47 11.1.1 IC Marking Information ........................................................................................ 47 11.1.2 Product Ordering Information............................................................................... 47 11.2 Soldering temperature profile .......................................................................................... 48
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XRS10L620
Rev 1.00
1. XRS10L620 Revision history
This document details the revision history for XRS10L620 and its derivatives as in Table1. Table 1. Revision History Release Day Revision 2008/09/29 2008/10/02 2008/01/20 0.10 0.11 1.00 Initial revision Remove target mode Release Description Notes
2. Overview
XRS10L620 is a 2ch-SATA 1ch-IDE controller with PCI-X interface. It can connect up to 4 devices at the same time, 2 SATA devices and 2 IDE/ATAPI devices. With its 32-bit PCI-X interface, it can easily with any MCU or CPU with PCI/PCI-X interface to form a powerful subsystem connecting high speed SATA storage devices and low cost IDE HD's and ODD's (optical disc drive). The excellent compatibility of XRS10L620 with IDE HD's and ODD's make it especially suitable to construct an enclosure device with both IDE HD's and CD-ROM/DVD-ROM or CD/DVD burners, such as external SATA/IDE raid box or CD/DVD copy machine. The two SATA channels on the chip can function in HOST mode. They comply with SATA Gen1 specification (Gen1 supports 1.5Gbps data rate) and Gen2 (3Gbps data rate) specification. As for the IDE channel, the maximum transfer rate range from 16.7 MB/s to 150 MB/s. Further more, data transfer can take place among 3 devices to PCIX bus simultaneously.
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Rev 1.00
3. Features
3-1 General 0.18um CMOS process technology Spread-Spectrum Clock (SSC) tolerance I2C interface operating in master/slave mode 2 SATA ports and 1 ATA/ATAPI port 1.8V/3.3V power supply 128-pin LQFP package 3-2 PCI-X Interface Compliant with PCI-X specifications Rev. 1.0a Compliant with PCI specification Rev 2.3 Compliant with PCI Bus Power Management Interface Specification Rev 1.1 32bit PCI-X with burst data rate 400MB/s at 100MHz maximum. Supporting Dual Address Cycle (DAC), break the 4GB memory limit. Supporting Enhanced AHCI to reduce CPU overhead All registers appear in memory and IO space Flash ROM interface setup utility and booting 3-3 SATA Interface Conforming to Gen1i/Gen1m (1.5Gb/s), capable of eSATA Supporting 2 SATA ports with 1.5Gb/s data rate on each port Supporting Hot Plug for devices on channels or behind the Port Multiplier Supporting Command-based switching (Port Multiplier 1.2) Supporting Asynchronous Notification Supporting Native Command Queuing (NCQ) - not combined with Port Multiplier Staggered spin-up control on 2 channels Individual device active LED indication I2C interface in master & slave role for SATA enclosure service 3-4 IDE Interface One IDE channel to support master and slave devices Conforming to ATA-7 specification Supporting PIO mode 0, 1 ,2, 3, 4 with 16.6MB/s data rate Supporting multiword DMA mode 0, 1, 2 with 16.6MB/s data rate Supporting Ultra DMA mode 0, 1, 2, 3, 4, 5, 6 with data rate up to 150MB/s Programmable active and recovery cycle register timing per device
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4. Block Diagram
Configuratio n Registers
Test Control
I2C Control
Flash Control
Flash ROM
Global and Channel Register PCIX Bus PCIX Arbitatio n
SATA Control IDE Port
IDE Bus
IDE FIFO
AHCI Control
SATA 0 PHY SATA 1
SATA Bus0 SATA Bus1
AHCI Control
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5. PIN DIAGRAM
5.1 XRS10L620 128-pin Diagram
AD18 AD17 AD16 BE2# FRAME# IRDY# GND TRDY# VDD33 DEVSEL# STOP# VDD18 PAR GND BE1# AD15 AD14 AD13 M66EN AD12 AD11 AD10 AD9 AD8 BE0# AD7
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
GND AD6 AD5 VDD33 AD4 AD3 AD2 AD1 AD0 GND TX1P TX1N GNDA VDDA3 RX1N RX1P VDDA4 VDDA1 RSVXO OSCI GNDA GNDA RX0P RX0N VDDA2 GNDA TX0N TX0P TESTMODE RCS# ROE#/LED0# RA2 RA0 GND RA1 VDD18 RWE# GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AD19 GND AD20 AD21 AD22 AD23 IDSEL BE3# AD24 AD25 GND AD26 VDD33 AD27 AD28 AD29 AD30 AD31 GND PREQ# PGNT# PCLK PRST# VDD18 INTA# DRST# DD7/RA3 DD8/RA4 DD6/RA5 GND DD9/RA6 VDD18 DD5/RA7 DD10/RA12 VDD33 DD4/RA15 DD11 DD3/RD7
XRS10L620
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
DD12/RD6 DD2/RD5 DD13/RD4 GND DD1/RD3 DD14/RD2 DD0/RD1 DD15/RD0 DDRQ DIOW# VDD18 DIOR# GND DCHRDY DACK#/RA14 DIRQ DSA1/RA13 DLLEN# DSA0/RA8 DSA2/RA9 VDD33 DCS0#/RA11 DCS1#/RA10 SCL/GIO3 SDA/GIO2 LED1#/GIO1
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XRS10L620 Rev 1.00 5.2 XRS10L620 Pin Assignment Pin# Name I/O Pin# IO IO IO IO IO IO IO O O Name I/O Pin# O/I O/I O/I Name I/O Pin# IO IO IO Name I/O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I IO IO IO IO IO IO IO
1 GND 2 AD6 3 AD5 4 VDD33 5 AD4 6 AD3 7 AD2 8 AD1 9 AD0 10 GND 11 TX1P 12 TX1N 13 GNDA 14 VDDA3 15 RX1N 16 RX1P 17 VDDA4 18 VDDA1 19 RSVXO 20 OSCI 21 GNDA 22 GNDA 23 RX0P 24 RX0N 25 VDDA2 26 GNDA 27 TX0N 28 TX0P 29 TESTMODE 30 RCS# 32 RA2 O O I O/I O/I I I O I I I
33 RA0 34 GND 35 RA1 36 VDD18 37 RWE# 38 GND
65 DD3/RD7 66 DD11 67 DD4/RA15 68 VDD33 69 DD10/RA12 70 DD5/RA7 71 VDD18 72 DD9/RA6 73 GND 74 DD6/RA5 75 DD8/RA4 76 DD7/RA3 77 DRST# 78 INTA# 79 VDD18 80 PRST# 81 PCLK 82 PGNT# 83 PREQ# 84 GND 85 AD31 86 AD30 87 AD29 88 AD28 89 AD27 90 VDD33 91 AD26 92 GND 93 AD25 94 AD24 95 BE3# 96 IDSEL
97 AD23 98 AD22 99 AD21 100 AD20
IO 101 GND IO 102 AD19 103 AD18 IO 104 AD17 105 AD16 IO 106 BE2# IO 107 FRAME# IO 108 IRDY# O O I I I O 109 GND 110 TRDY# 111 VDD33 112 DEVSEL# 113 STOP# 114 VDD18 115 PAR 116 GND IO 117 BE1# IO 118 AD15 IO 119 AD14 IO 120 AD13 IO 121 M66EN 122 AD12 IO 123 AD11 124 AD10 IO 125 AD9 IO 126 AD8 IO 127 BE0# I 128 AD7
39 LED1#/GIO1 IO 40 SDA/GIO2 41 SCL/GIO3 IO IO
42 DCS1#/RA10 O/I 43 DCS0#/RA11 O/I 44 VDD33 45 DSA2/RA9 46 DSA0/RA8 47 DLLEN# 48 DSA1/RA13 49 DIRQ 51 DCHRDY 52 GND 53 DIOR# 54 VDD18 55 DIOW# 56 DDRQ 57 DD15/RD0 58 DD0/RD1 59 DD14/RD2 60 DD1/RD3 61 GND 62 DD13/RD4 63 DD2/RD5 64 DD12/RD6 IO IO IO O I IO IO IO IO O O/I O/I I O/I I I
50 DACK#/RA14 O/I
31 ROE#/LED0# O
**`O/I' input function available only when PRST# active.
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XRS10L620 Rev 1.00 5.3 Pin Descriptions 5.3.1 PCI interface Pin Name
AD[31:0]
Pin#
85-89,91,93,94, 97-100,102-105, 118-120,122-126, 128,2,3,5-9
Type
Description
I/O PCI Multiplexed Address and Data
BE[3:0]# PAR FRAME# TRDY# IRDY# STOP# DEVSEL# IDSEL INTA# PREQ# PGNT# PCLK PRST# M66EN
95,106,117,127 115 107 110 108 113 112 96 78 83 82 81 80 121
I/O PCI Command/Byte Enable I/O PCI Parity I/O PCI Cycle Frame I/O PCI Target Ready I/O PCI Initiator Ready I/O PCI Stop I/O PCI Device Select I O O I I I I PCI Initialization Device Select PCI Interrupt Request A PCI Master Request PCI Master Grant PCI Clock PCI Reset PCI 66MHz indication
5.3.2 Serial ATA interface Pin Name
RSVXO OSCI
Pin#
19 20
Type
O I
Description
Reserved for internal test. External oscillator input. The clock rate is 25MHz, 1.8V level.
TX0P TX0N RX0N RX0P RX1P RX1N TX1N TX1P 7
28 27 24 23 16 15 12 11
O O I I I I O O
SATA 0 positive output of the differential signal SATA 0 negative output of the differential signal SATA 0 positive input of the differential signal SATA 0 positive input of the differential signal SATA 1 positive input of the differential signal SATA 1 positive input of the differential signal SATA 1 negative output of the differential signal SATA 1 positive output of the differential signal
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5.3.3 Parallel ATA interface Pin Name
DCS1#/RA10 DCS0#/RA11 DSA2/RA9 DSA0/RA8 DSA1/RA13 DIRQ DACK#/RA14 DCHRDY DIOR# DIOW# DD[15:0]
Pin#
42 43 45 46 48 49 50 51 53 55 57,59,62,64, 66,69,72,75, 76,74,70,67, 65,63,60,58
Type
O/I IDE chip select 1 O/I IDE chip select 0 O/I IDE address2 O/I IDE address0 O/I IDE address1 I IDE interrupt
Description
O/I IDE DMA acknowledge I O O IO channel ready or DDSTROBE, DDMARDY# IO read or HSTROBE, HDMARDY# IO write or STOP
I/O IDE data bus
DRST#
77
O
IDE reset
5.3.4 Flash ROM pins (some are shared with IDE bus pins) : Pin Name
RCS# ROE#/LED0# RWE# RA0 RA1 RA2 DD7/RA3 DD8/RA4 DD6/RA5 DD9/RA6 DD5/RA7 DSA0/RA8 DSA2/RA9 DCS1#/RA10 8
Pin#
30 31 37 33 35 32 76 75 74 72 70 46 45 42
Type
O/I O/I O/I O/I O/I O/I I/O I/O I/O I/O I/O O/I O/I O/I ROM chip select
Description
ROM output enable and SATA0 LED# ROM write enable ROM address 0 ROM address 1 ROM address2 ROM address3 ROM address4 ROM address5 ROM address6 ROM address7 ROM address8 ROM address9 ROM address10
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DCS0#/RA11 DD10/RA12 DSA1/RA13 DACK#/RA14 DD4/RA15 DD15/RD0 DD0/RD1 DD14/RD2 DD1/RD3 DD13/RD4 DD2/RD5 DD12/RD6 DD3/RD7 43 69 48 50 67 57 58 59 60 62 63 64 65 O/I I/O O/I O/I I/O I/O I/O I/O I/O I/O I/O I/O I/O ROM address11 ROM address12 ROM address13 ROM address14 ROM address15 ROM data0 ROM data1 ROM data2 ROM data3 ROM data4 ROM data5 ROM data6 ROM data7
5.3.5 Miscellaneous : Pin Name
LED1#/GIO1 SDA/GIO2
Pin#
39 40 41 47 29
Type Description
I/O I/O I/O I I SATA channel 1 LED and general IO pin I2C bus signal and general IO pin, internally pull up I2C bus signal and general IO pin, internally pull up Internal test only Reserved, connected to GND normally
SCL/GIO3
DLLEN# TESTMODE
5.3.6 Power : Pin Name
VDD18 VDD33 VDDA4,VDDA3, VDDA2,VDDA1 GND 1,10,34,38,52,61, 73, 84,92,101,109,116 GNDA 13,21,22,26
Pin#
36,54,71,79,114 4,44,68,90,111 17,14,25,18
Type Description
1.8V Digital 1.8V core power 3.3V Digital 3.3V IO power 1.8V Analog 1.8V power supply. Each is connected to the series ferrite bead for noise suppression. Digital ground, Each pin must have solid connection with PCB GND plane by at least 2 vias or other traces with it. Analog ground
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5.3.7 Hardware configuration jumper setting : ( All pins are pulled high or low in chip, 1 = pull high; 0 = pull low) Pin Name Pin# Default
RA1,RA0 35,3 3 1,1 PCI Device ID numbers : 1,1 = `000D'H 1,0 = `000E'H 0,1 = `000F'H 0,0 = `000D'H, reserved for internal test RA2 32 1 0 = Enable staggered spin-up operation PCI-reset will not issue COMRESET to all SATA channels. HDDs spin- up are initiated by software 1= Disable staggered spin-up operation. PCI-reset will issue COMRESET to all SATA channels and spin up all SATA HDDs PCI SubClass number : 1= 00H (SCSI) 0= 04H(RAID) DCS1#/RA10 42 48 45 1 Reserved for internal test. 1= fix phase DSA1/RA13 DSA2/RA9 1 1 Lowest address bit of I2C master (SEMB), high 6 bit = 101000B Both SATA channels TX driver initial level 0 = 500mV mode for Gen1i during initialization 1 = 550mV mode for Gen1m during initialization Other TX levels of each channel can be programmed by software DSA0/RA8 46 30 37 50 1 1= forced Gen1 speed for SATA channel 0 0=Normal speed negotiation, for internal test only RCS# 1 1= forced Gen1 speed for SATA channel 1 0=Normal speed negotiation, for internal test only RWE# DACK#/RA14 1 1 1 = SATA0 is Host mode (default) 1 = SATA1 is Host mode (default)
Description
DCS0#/RA11,
43
1
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6. Register Definition
6.1 PCI Configuration Memory Registers : ( RWC : write 1 to clear ) ( RW1 : write 1 to enable the bit and will be auto-cleared; Addr
00,01 02,03 04,05
write 0 has no function )
R/W
R R RW
Name
Vendor ID Device ID Command Register 1191h
Description
000Dh, 000Eh, 000Fh, depend on RA1,0 setting Bit0 = 1 : enable IO space = 0: disable IO space Bit1 = 1 : enable Memory space = 0: disable Memory space Bit2 = 1 : enable Bus Master = 0: disable Bus Master Bit6 = 1 : enable Parity error response = 0: disable Parity error response Bit10 = 1 : disable INTA# = 0: enable INTA# Other bits are `0', read only Bit3 = reflect the interrupt status Bit4 = 1 : with PCI power management capability Bit5 = 1 : 66 MHz capable Bit7 = 0 : Fast Back to Back Capable Bit8 = 1 : Data parity error detected by master Bit10,9 = 0,1 : medium DEVSEL timing Bit13 = 1 : Received Master abort Bit15 = 1 : Detected parity error by device 00h
06,07
R
Status Register
08 09 0A 0B 0C 0D 0E 0F 10-13
R R R R RW RW R R RW
Revision ID
Programming Interface 00h SubClass Basic Class Cache Line Size Latency Timer Header type BIST Base Addr Reg0 00H (SCSI) or 04H(RAID), by DCS0#/RA11 configuration 01h, mass storage 00h (00h, default) The register specify PCI clock count for this PCI master 00h 00h IO address of Global host & IDE registers, length 256 bytes
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11
14-17
RW
Base Addr Reg1
18-1B
RW
Base Addr Reg2
1C-1F
RW
Base Addr Reg3
20-23
RW
Base Addr Reg4
24-27
RW
Base Addr Reg5
28-2B 2C-2F
R R/W
Card CIS Pointer
bit0 : fixed to 1 bit[7:1] : fixed to 0 other bits are read/writable IO address of SATA channel 0 & 1 registers, length 256 bytes bit0 : fixed to 1 bit[7:1] : fixed to 0 other bits are read/writable IO address reserved for test, length 256 bytes bit0 : fixed to 1 bit[7:1] : fixed to 0 other bits are read/writable IO address reserved for test, length 256 bytes bit0 : fixed to 1 bit[7:1] : fixed to 0 other bits are read/writable IO address reserved for test, length 256 bytes bit0 : fixed to 1 bit[7:1] : fixed to 0 other bits are read/writable MEM address of Global and all SATA channels registers, length 1280 bytes. The Memory accessed registers are the same as those mapped by Base Addr [4:0]. bit[11:0] : fixed to 0, in 4KB range other bits are read/writable 00000000h
XRS10L620 Rev 1.00
Subsystem Vendor ID Default are same as Vendor ID and Device ID Subsystem Device ID Expansion ROM Base bit0 : read/writable, set 1 to enanble the ROM bit[15:1] : fixed to 0 Address bit[31:16] : read/writable (40h) point to power management link list Cap_Pointer Reserved Interrupt line Interrupt pin Min_GNT Max_LAT 00h 00h 01h, INTA# 08h, specify a burst period in 250ns unit 0Dh, specify how often the device needs to gain access the PCI bus in 250ns unit Refer to section (2.1)
30-33
R/W
34 35-3B 3C 3D 3E 3F
R R RW R R R
40 to 47
RW
PCI power management registers
48 to 4F
RW
PCI-X Capabilities List Refer to section (2.2) Item
6.1.1 PCI Power Management Registers : CFGM+40h to 47h : 8 bytes PCI power management registers CFGM+40h (R): Capability ID, default 01H CFGM+41h (R): Next Item Pointer, default 48H
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XRS10L620 Rev 1.00 CFGM+42h,43h(R) : Power Management capabilities(PMC), default 0602H CFGM+44h,45h(RW) : Power Management Control/Status Register(PMCSR)
Default 0000H Bit [15:02]: all 0h, read only Bit1,bit0 : Power State, read/write 00b is D0 state 01b is D1 state 10b is D2 state 11b is D3 hot state
CFGM+46h(R) : PMCSR_BSE register, default 00H CFGM+47h(R) : Data register, default 00H 6.2 PCI-X Capabilities List Item : CFGM+48h(R) : PCI-X capabilities ID, = 07h. CFGM+49h(R) : Next Capability, = 00h CFGM+4Ah(RW) : 16 bits PCI-X command register Bit(s) R/W default
15,14 R 00 Reserved PCI-X Capabilities List Item Version. 13,12 R 00 `00' means Version 0, without ECC support and Capabilities List Item size is 8 bytes 11:7 R 00000 Reserved Maximum Outstanding Split Transactions. 6:4 RW 010 `010' means Maximum Outstanding at one time as a requester is 3. Values below`010' means 1 outstanding only. Other values are same as `010'. Maximum Memory Read Byte Count. 3,2 RW 01 `01' means Maximum byte count is 1024 for burst memory commands `00' means Maximum byte count is 512 for burst memory commands Other values are same as`01'. 1 R 0 Enable Relaxed Ordering `0': The device never set the Relaxed Ordering attribute bit Uncorrectable Data Error Recovery Enable.
Description
0
RW
0
6.2.1 CFGM+4Ch(R) : 32 bits PCI-X Status Register Bit(s) R/W default Description
31 13 R 0 0 = PCI-X 533 not capable
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30 R 0 0 = PCI-X 266 not capable (Not a PCI-X mode 2 device) Received Split Completion Error Message. 29 RWC 0 0 = No Split Completion error message received. 1 = A Split Completion error message has been received. Designed Maximum Cumulative Read Size `010' is 4KB(32 ADQs) cumulative outstanding when Maximum Memory 28:26 R 010 Read Byte Count register is assigned to 1024 bytes. `001'is 2KB(16 ADQs) cumulative outstanding when Maximum Memory Read Byte Count register is assigned to 512 bytes. 25:23 R 010 Designed Maximum Outstanding Split Transactions. `010' means Maximum Outstanding at one time as a requester is 3. Designed Maximum Memory Read Byte Count. `01' means Maximum byte count is 1024 for burst memory commands Device Complexity 0 = simple device 1 = bridge device
22,21
R
01
20
R
0
Unexpected Split Completion 19 RWC 0 0 = No unexpected Split Completion has been received. 1 = An unexpected Split Completion has been received. Split Completion Discarded. 18 RWC 0 0 = No Split Completion has been discarded. 1 = A Split Completion has been discarded. 17 16 R R 1 0 1 = The device's maximum clock frequency is 133 MHz. 0 = The bus is 32 bits wide. Bus Number. 15:8 R FFh Each time the function is addressed by a Configuration Write transaction, it will update the register with the contents of AD[7:0] of the attribute phase of the Configuration Write. Device Number. 7:3 R 1Fh Each time the function is addressed by a Configuration Write transaction, it will update the register with the contents of AD[15:11] of the attribute phase of the Configuration Write. 2:0 R 000 Function Number
6.3 Host Registers definition: ( IOG = global, pointed by PCI Base Address Reg0 ) ( IO01 = channel0&1, pointed by PCI Base Address Reg1 ) ( IO23 = channel2&3, pointed by PCI Base Address Reg2, Reserved ) ( IO45 = channel4&5, pointed by PCI Base Address Reg3, Reserved )
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Register Table Register addr IO addr mapping MEM addr mapping
[13 : 00] [7F : 14] [9F : 80] [FF : A0] [17F : 100] [1FF : 180] IOG+ [13 : 00] IOG+ [7F : 14] IOG+ [9F : 80] IOG+ [FF : A0] IO01+ [7F : 00] IO01+ [FF : 80] MEM5+ [13 : 00] MEM5+ [7F : 14] NA MEM5+ [FF : A0] MEM5+ [17F : 100] MEM5+ [1FF : 180]
Description
AHCI generic host control Reserved IDE channel registers I2C, GIO, PHY, Test registers AHCI SATA Channel 0 registers AHCI SATA Channel 1 registers
6.3.1 Global host registers : (IOG + 00h to 0FFh) Reg_000H (IOG+00h) : Host Capability (CAP) Bit(s) R/W default Symbol
31 30 29 28 27 26 25 24 23:20 19 18 17 16 15 14 13 12:08 07:05 04:00 R R R R R R R R R R R R R R R R R R R 1 1 0 0 RA2 depends 0 1 1 0010 0 1 1 0 0 1 1 11111 0 00001 S64A SNCQ SIS SSS SALP SAL SCLO ISS SNZO SAM SPM PMD SSC PSC NCS NP
Description
Support 64-bit Addressing Support Native Queue Reserved Support Interlock Switch 1 = support Stagger Spin-up default =0, if RA2 pull up default =1, if RA2 pull down Support Aggressive Link Power Management Support Active LED Support Command List Override Interface Speed Support. Support Non-zero DMA offsets Support AHCI mode only, no legacy mode Support Port Multiplier, FIS base switching Reserved Only support single DRQ block data transfer for PIO Slumber state capable Partial state capable Support 32 command slots per channel Reserved Support maximum of 2 ports
Reg_004H (IOG+04h) : Global HBA Control (GHC) Bit(s) R/W default Symbol
31 15 R 1 AE
Description
Software can only access the chip using AHCI
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30:02 01 R RW 0 0 IE Reserved Interrupt Enable 0 = INTA# disabled for all interrupt from all ports 1 = INTA# enabled, if CFGM+4 bit10 =0 also HBA internal reset, issued by SW and auto-cleared when reset completed. SW should set`1'once for power on initialization. If Reg_000H bit 27(SSS)=0, COMRESET issued to all ports. If SSS=1, no COMRESET issued, SW need to spin-up each port after the reset has completed. The bit is self-cleared after reset action completed
00
RW1
0
HR
Reg_008H (IOG+08h) : Interrupt Status Register (IS) Bit(s) R/W default Symbol
31 30 29 28:09 08 07:02 01:00 R RWC RWC R R R R 0 0 0 0 0 0 00b
Description
Interrupt flag when as I2C slave, means one byte received IFS completed via I2C. Cleared when Reg_0B0H RXRS is read out Interrupt flag when as I2C master, means one byte transfer IFM completed via I2C. The interrupt is cleared as below : Master receive : Read out Reg_0B0H RXRM. Timer IRQ flag, 1=timer up Set 1 will clear this flag and timer IRQ signal (INTA#) Reserved to 0 Latched IDE IRQ flag, reflect the Reg_090H bit 18 when IDEPS Reg_090H bit 11 = 1 Reserved to 0 If set, the corresponding bit map port has at least an interrupt flag IPS in P0IS, P1IS, and their P0IE, P1IE are enabled respectively. Each bit is cleared when all flags in respective PxIS are cleared
Reg_00CH (IOG+0Ch): Ports Implemented Bit(s) R/W default Symbol
31:02 01:00 R R 0 11b PI
Description
=1, the bit significant port is available. =0, the bit significant port is not available
Reg_010H (IOG+10h) : AHCI Version (VS) Bit(s) R/W default Symbol
31:16 15:00 R R 0001h 0000h MJR MNR Major version is `1' Minor version is`0'
Description
Reg_014H to Reg_07FH are reserved. Reg_080H to Reg_087H (IOG+80h to 87h) :
Reg_80h to 87h are mapped to standard Parallel IDE port 0 to port7 16
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(The region is only IO port accessed, not available by memory access using MEM5 decoding)
Reg_088H to Reg_08DH (IOG+88h to 8Dh) : (RO)
Reserved to 00h
Reg_08EH (IOG+8Eh) :
Standard Parallel IDE alternate status and control register
Reg_08FH (IOG+8Fh) : (RO)
Reserved to 00h
Reg_090H (IOG+90h) : IDE DMA start/stop Bit(s) R/W default
31 RW 0 Test only for CH0 and CH1. FIFO threshold to initiate PCI write request for IDE channel 000 : 7/8 FIFO full, 30:28 RW 000 001 : 6/8 FIFO full, 010 : 5/8 FIFO full, 011 : 4/8 FIFO full, 27 R 0 Reserved FIFO threshold to initiate PCI read memory request for IDE channel 000 : 7/8 FIFO empty, 26:24 RW 000 001 : 6/8 FIFO empty, 010 : 5/8 FIFO empty, 011 : 4/8 FIFO empty, 23:20 19 18 17 16 15 14 13 12 11 R R RWC RW R RW RW R R RW 0000 0 0 0 0 0 0 0 0 0 Reserved for internal test IDE FIFO`NOT empty' flag, 0 means empty Latched IDE IRQ flag and also shown at Reg_008H bit8, fill 1 to clear the bit, or cleared when IDE IRQ is cleared. IDE IOR/W split enable, 1 = split enable PCI/PCIX IDE DMA is active Set 1 to output low to reset IDE; 0 to normal state Set 1 to disable all IDE pins output Reserved Reserved for DLLEN# pin 1= enable IDE IRQ as PCI INTA# signal. Default 0=disable 100 : 3/8 FIFO empty 101 : 2/8 FIFO empty 110 : 1/8 FIFO empty 111 : 1/8 FIFO empty 100 : 3/8 FIFO full 101 : 2/8 FIFO full 110 : 1/8 FIFO full 111 : 1/8 FIFO full
Description
17
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XRS10L620 Rev 1.00
PCI/PCIX mode indicator Bit 8 , 1= PCIX66 mode 10:8 R Bit 9 , 1= PCIX100 mode Bit 10 , 1= PCIX133 mode Bit (10,9,8)= (0,0,0) means PCI mode 7:4 3 2,1 0 R RW R RW 00h 0 00 0 Reserved IDE DMA direction, 1 = write to host memory Reserved Start/Stop PCI IDE DMA
Reg_094H (IOG+94h): IDE speed Bit(s) R/W default
31 R 0 Reserved Slave-IDE UDMA mode# +1, 000= disable UDMA, enable NDMA; 30,29,28 RW 000 001=UDMA mode 0 010= UDMA mode 1 011= UDMA mode 2 27 R 0 Reserved Master-IDE UDMA mode# +1, 000= disable UDMA, enable NDMA; 26,25,24 RW 000 001=UDMA mode 0 010= UDMA mode 1 011= UDMA mode 2 23 22:20 R RW 0 111 Reserved 8 bit IDE ports speed, active cycles clocks (1 clk=26.7ns) 000 = 8 clk, 001=1 clk, . . . . . . . . . .,110=6 clk, 111=12clk 8 bit IDE ports speed, recovery cycles clocks (1 clk=26.7ns) 0000= 12 clk, 0001=1 clk, . . . . . . ,1011=11 clk, 11xx=15clk Reserved slave 16 bit IDE PIO/NDMA data active cycle clocks (1 clk=26.7ns) 000 = 8 clk, 001=1 clk, . . . . . . . . . .,110=6 clk, 111=12clk slave 16 bit IDE PIO/NDMA data recovery cycle clocks (1 clk=26.7ns) 0000= 12 clk, 0001=1 clk, . . . . . . ,1011=11 clk, 11xx=15clk Reserved ; ; ; 100= UDMA mode 3 101= UDMA mode 4 110= UDMA mode 5 111= UDMA mode 6 ; ; ; 100= UDMA mode 3 101= UDMA mode 4 110= UDMA mode 5 111= UDMA mode 6
Description
19:16 15 14:12
RW R RW
0000 0 000
11:08 07
RW R
0000 0
18
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XRS10L620 Rev 1.00
06:04 RW 000 master 16 bit IDE PIO/NDMA data active cycle clocks (1 clk=26.7ns) 000 = 8 clk, 001=1 clk, . . . . . . . . . .,110=6 clk, 111=12clk master 16 bit IDE PIO/NDMA data recovery cycle clocks (1 clk=26.7ns) 0000= 12 clk, 0001=1 clk, . . . . . . ,1011=11 clk, 11xx=15clk
03:00
RW
0000
Reg_098H (IOG+98h) :
Low Dword address of Parallel IDE PRD pointer
Bit(s) R/W default
31:02 01:00 RW R 0 0
Description
Low Dword address of Parallel IDE PRD pointer Fixed to 0
Reg_09CH (IOG+9Ch) :
High Dword address of Parallel IDE PRD pointer
Bit(s) R/W default
31:00 RW 0
Description
High Dword address of Parallel IDE PRD pointer
Reg_0A0H (IOG+A0h) : Flash ROM data port
Access to the port will start ROM control signals 4 times, in/out the 8-byte ROM data bus with address bus defined in Reg_0A8H.
Bit(s) R/W default Symbol
31:24 23:16 RW RW RW RW
Description
Flash ROM data port byte 3 Flash ROM data port byte 2
15:08 07:00
Flash ROM data port byte 1 Flash ROM data port byte 0
Reg_0A4H (IOG+A4h) : GIO control Bit(s) R/W default Symbol Description
Function switch for GIO3 pin 00 = normal function, as SCL 01 = output user defined bit(bit23) to GIO3 31:30 RW 00 10 = output one SATA channel debug signal to GIO3, see Reg_150H and Reg_1D0H 11 = output disabled, pure input mode Set 1 to negate other share pins function (like SCL, SDA, LED1Z, LED0Z), and dedicated as GIO pin(s)
19
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XRS10L620 Rev 1.00
Function switch for GIO2 pin 00 = normal function, as SDA 01 = output user defined bit(bit22) to GIO2 29:28 RW 00 10 = output one SATA channel debug signal to GIO2, see Reg_150H and Reg_1D0H 11 = output disabled, pure input mode Set 1 to negate other share pins function (like SCL, SDA, LED1Z, LED0Z), and dedicated as GIO pin(s) Function switch for GIO1 pin 00 = normal function, as LED1# 01 = output user defined bit(bit21) to GIO1 27:26 RW 00 10 = output one SATA channel debug signal to GIO1, see Reg_150H and Reg_1D0H 11 = output disabled, pure input mode Set 1 to negate other share pins function (like SCL, SDA, LED1Z, LED0Z), and dedicated as GIO pin(s) 25:24 23:21 20 19:17 16 15 14:01 RW RW RW R R RW R 0 0 0 00 000 0 Reserved User defined output value of GIO[3:1] pins, 1 to output high Available if modes in bit[31:26] are enabled respectively Reserved GIO[3:1] pins input value respectively Available if modes in bit[31:26] are switched to input mode Reserved 1=GIO3 pin always output 1KHz signal when bit[31:30]= `01' Reserved Switch one SATA channel for output debug signals to GIO pin 00 RW 0 0 = SATA channel 0 1 = SATA channel 1
Reg_0A8H (IOG+A8h) : PCI Bus Control and ROM Address Bit(s) R/W default Symbol
31:18 RW 0
Description
The corresponding RA[15:2] pins value, set 0/1 will output low/high, available if bit16(PIOROM) is enabled to `1'. Reading of the bits reflect the real pins value. Reserved
17
R
0
20
1/20/2009
XRS10L620 Rev 1.00
1=Enable PIOROM and also disable IDE function 16 RW 0 RA[15:2] output are controlled by bit [15:2] of this register RA[1:0] are auto-generated by chip 15:13 12 11 10 09 08 07 R RW RW R/W RW RW 0 0 0 0 0 0 Reserved 1= enable UDMA150, when Reg_094H is also set to UDMA mode 6 on that channel. Test only. 1= delayed write strobe Test only, set 1 to disable DAC 1 to issue DAC in every Memory access command, test only. 0: Rolling PCI arbitration on all channels 1: Fixed PCI retry arbitration on all channels M66EN pin value
R
0
06
RW
0
1 : Enable periodical issuing COMRESET on SATA channels when their PHY are not ready 1 : For PCIX, forced Memory Write command instead of Memory Write Block command Reserved 1 : Disable Write SubSystem ID 1 : Enable PCI burst 1 : Enable PCI Memory Read Multiple Reserved for PCI(X) 64 bit transfer
05 04 03 02 01 00
RW RW RW RW RW R
0 0 0 1 1 0
Reg_0ACH (IOG+ACh) : Timer Control Bit(s) R/W default Symbol
31:24 23,22 21:20 18 17 16 15 14:0 R R R RW1 RW1 RW RW1 RW 0 00 00 0 0 0 0 0 Reserved Test only, Mem1 result, `11'= good, other values= error Test only, Mem0 result, `11'= good, other values= error TSTM1 Test only. Start to test Mem1 TSTM0 Test only. Start to test Mem0 1 : Enable timer IRQ as INTA# signal `1'= start timer. The bit is auto-cleared when timer counts to 0 15 bit timer count, in unit of 4 ms. Auto decrement to 0, when timer starts.
Description
Reg_0B0H (IOG+B0h) : I2C Bus Control Bit(s) R/W default Symbol
21
1/20/2009
Description
XRS10L620 Rev 1.00
31:24 23:16 15:08 07 06 05 04 03 02 01 00 R R W W W W W W RW RW R 00h 00h RXRS As Slave, last byte received via I2C RXRM As Master, the byte content received via I2C TXR STA STO RD WR AC IFS IFM TIP As Master, the byte content to transmit via I2C Generate START condition Generate STOP condition As Master, read from slave As Master, write to slave ACK, when as receiver, `0' to sent ACK, `1' sent NACK Enable interrupt flag (Reg_008H bit 31) to INTA# when as slave Enable interrupt flag (Reg_008H bit 30) to INTA# when as master `1'=Transfer In Progress; `0'=transfer complete
Reg_0B4H (IOG+B4h) : Reserved
Test only for 32 bit seed value
Reg_0B8H to Reg_0FFH (IOG+B8h to FFh ) : Reserved 6.3.2 Port Registers (length 80h bytes per port/channel): SATA Port 0 address = Reg_100H to Reg_17FH =(IO01+00h to 7Fh) SATA Port 1 address = Reg_180H to Reg_1FFH =(IO01+80h to FFh) Reg address from offset
00 - 03 04 - 07 08 - 0B 0C - 0F 10 - 13 14 - 17 18 - 1B 1C - 1F 20 - 23 24 - 27 28 - 2B 2C - 2F 30 - 33 34 - 37
Symbol PxCLB PxCLBU PxFB PxFBU PxIS PxIE PxCMD PxTFD PxSIG PxSSTS PxSCTL PxSERR PxSACT
Description
Port x command list base address Port x command list base address upper 32bits Port x FIS base address Port x FIS base address upper 32bits Port x interrupt status Port x interrupt enable Port x command
PxPRBS40B_PAT User defined pattern for internal test
Port x task file data Port x signature Port x SCR0: SStatus Port x SCR1: Scontrol Port x SCR2: Serror Port x SCR3: Sactive
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XRS10L620 Rev 1.00
38 - 3B 3C - 3F 40 - 43 44 - 47 48 - 5F 48 - 4B 4C - 4F 50 - 53 54 - 57 58 - 5B 5C - 5F 60 - 63 64 - 67 68 - 6B 6C - 6F 70 - 73 74 - 77 78 - 7B 7C - 7F
PxCI PxNOTIF PxCICLR PxSDBFG PxDebug0 PxDebug1 PxPHYCTRL PxPLLTEST PxTxTEST PxRxTEST PxTFD1 PxTFD23 PxTFD45 PxTFD67 PxAIS PxAIE PxAUFS
Port x command issue Port x Notification bits from devices behind P.Multiplier Clear Port x CI/SACT bits by host 32 Act bits of Set Device Bits FIS Registers for internal test Debug port 0 Debug port 1 Physical Layer Control Register PLL Parameters Tx Parameters Rx Parameters MultiPM mode, Port x task file for Port Multiplier #1 MultiPM mode, Port x task file for Port Multiplier #2,#3 MultiPM mode, Port x task file for Port Multiplier #4,#5 MultiPM mode, Port x task file for Port Multiplier #6,#7 Port x additional interrupt status, for PM #1 to 7 Port x additional interrupt enable, for PM #1 to 7 Port x Unknown FIS interrupt status and enable, for PM #1 to 7 Reserved.
Reg_100H (IO01+00h) : P0CLB Bit(s) R/W default Symbol
31:10 09:00 RW R 0 0 CLB 1024 bytes aligned Reserved
Description
Lower 32 bit base physical address of the command list,
Reg_104H (IO01+04h) : P0CLBU Bit(s) R/W default Symbol
31:00 RW 0 CLBU
Description
Upper 32 bit base physical address of the command list
Reg_108H (IO01+08h) : P0FB Bit(s) R/W default Symbol
31:08 07:00 RW R 0 0 FB 256 bytes aligned Reserved
Description
Lower 32 bit base physical address of the received FISes,
Reg_10CH (IO01+0Ch) : P0FBU
23
1/20/2009
XRS10L620 Rev 1.00 Bit(s) R/W default Symbol
31:00 RW 0 FBU
Description
Upper 32 bit base physical address of the received FISes
Reg_110H (IO01+10h) : P0IS, interrupt status Bit(s) R/W default Symbol
31 30 R RWC 0 0 CPDS TFES Task file error status 1 = error bit of status register is updated by the device and set. Host bus fatal error status 1 = PCI target or master abort Host bus data error status 1 = PCI parity error detected Interface fatal error status 1 : The transfer is stopped due to SATA data FIS error Interface non-fatal error status 26 RWC 0 INFS 1 = SATA non-data FIS error, but was able to continue by internal retry 25 24 RWC RWC 0 0 UFSFG Do not use OFS Overflow status HBA receive more bytes from a device than those in PRD Incorrect port multiplier status Always 0 Reflect the value of PxSERR.N bit 1 = PhyRdy signal changed Reserved Represent PM# bit map, which has SDB FIS interrupt with `I'=1 16:09 RWC 0 and all 32 bits SACT are zero. Bit[16:9] map to PM#[7:0], while PM#[15:8] are overlapped in bit 9 08 07 06 05 R R R RWC 0 0 0 0 NOTIS `OR'ed flag of 16 bits at Reg_13Ch bit[15:0] DIS PCS DPS Device interlock switch status, reserved to 0 Reflect the value of PxSERR.X bit 1 = new ComInit comes Flag indicates all PRD data of a command table are transferred
Description
Cold detect status, reserved to 0
29
RWC
0
HBFS
28
RWC
0
HBDS
27
RWC
0
IFS
23
RWC
0
IPMS
22 21:17
R R
0 0
PRCS
24
1/20/2009
XRS10L620 Rev 1.00
If MultiPM bit (Reg_174H bit 1)=0, 04:00 00000 bit 4 and bit[2:0] fields are available for all If MultiPM bit (Reg_174H bit 1)=1, bit 4 and bit[2:0] fields are dedicated for PM#0 only 04 R 0 UFS Unknown FIS interrupt, when the FIS is copied to memory This bit is cleared by clearing PxSERR.DIAG..F bit `OR'ed flag of 40 bits of this register bit[16:9] and Reg_144h[31:0] about Set Device Bits FIS interrupts DMA setup FIS interrupt : This FIS is received with `I'bit set and has been copied into system memory PIO setup FIS interrupt : This FIS is received with `I' bit set, it and its related data are all transferred D2H register FIS interrupt : This FIS is received with `I' bit set and has been copied into system memory PM#0 to #15
03
R
0
SDBS
02
RWC
0
DSS
01
RWC
0
PSS
00
RWC
0
DHRS
Reg_114H (IO01+14h) : P0IE, interrupt enable of second layer
First layer enable are the CFGM+4 bit 10 and GHC.IE bit
Bit(s) R/W default Symbol
31 30 29 28 27 26 25 24 23 22 21:09 08 07 06 05 04 03 02 25 RW RW RW RW RW RW R RW RW RW R RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFE IPME PRCE CPDE TFEE HBFE HBDE IFE INFE
Description
If set, INTA# issued when P0IS.CPDS is set If set, INTA# issued when P0IS.TFES is set If set, INTA# issued when P0IS.HBFS is set If set, INTA# issued when P0IS.HBDS is set If set, INTA# issued when P0IS.IFS is set If set, INTA# issued when P0IS.INFS is set Reserved If set, INTA# issued when P0IS.OFS is set If set, INTA# issued when P0IS.IPMS is set If set, INTA# issued when P0IS.PRCS is set ("N" bit) Reserved
NOTIE If set, INTA# issued when P0IS.NOTIS is set. DIE PCE DPE UFE SDBE DSE If set, INTA# issued when P0IS.DIS is set If set, INTA# issued when P0IS.PCS is set ("X" bit) If set, INTA# issued when P0IS.DPS is set (data completed) If set, INTA# issued when P0IS.UFS is set (Unknown FIS) If set, INTA# issued when P0IS.SDBS is set If set, INTA# issued when P0IS.DSS is set
1/20/2009
XRS10L620 Rev 1.00
01 00 RW RW 0 0 PSE DHRE If set, INTA# issued when P0IS.PSS is set If set, INTA# issued when P0IS.DHRS is set
Reg_118H (IO01+18h) : P0CMD, Port 0 control, capability and flag Bit(s) R/W default Symbol Description
Interface communication control Host use the field to control SATA power management if the Link layer is in L_IDLE state, and no effect if not in the state 31:28 RW 0h ICC Fh - 7h & 5h - 3h : Reserved 6h : HBA request a transition to the Slumber state 2h : HBA request a transition to the Partial state 1h : HBA request a transition to the Active state 0h : No-op/Idle. If software read this value, it is allowed to issue the above power management control. HBA will perform the above controls and update this field back to idle(0h). Reserved for aggressive slumber /partial Reserved for aggressive link power management enable Drive LED on ATAPI Enable 1=always drive LED regardless of PxCMD.ATAPI bit When set, the connected device of the port is an ATAPI 1=this SATA port is Host mode; default value depend on RWE#(SATA0) or RA14(SATA1). Reserved CPD ISP HPCP PMA CPS 0=Cold presence detection disable Reserved to 0, 0= NOT support an interlock switch 1=hot plug capable Port Multiplier attached, detected and set by software Reserved
27 26 25 24 23 22:21 20 19 18 17 16
R R RW RW R R R R R RW R
0 0 0 0 RWE#(0) RA14(1) 0 0 0 1 0 0
ASP ALPE DLAE ATAPI TGTZ
26
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XRS10L620 Rev 1.00
15 R 0 CR Command list running, Indicates command list DMA engine of this port is running FIS receive running, Indicates FIS receive DMA engine of this port is running Reserved Current working command slot number in one of P0CI Reserved 0 = normal reset level of ST (bit0) 1 = deeper reset level of ST, issue COMRESET on the channel FIS receive enable, 04 RW 0 FRE `1' will post received FIS to host memory pointed by PxFB. Software must not set the bit until PxFB is a valid pointer. Command list override, set the bit will clear PxTFD.STS.BSY and PxTFD.STS.DRQ so that software reset could be issued regardless 03 RW1 0 CLO BSY and DRQ bit value. The bit is auto-cleared to 0 when BSY & DRQ are cleared. Writing the bit with 0 has no effect. Host mode only. 02 R 1 POD Power on device, reserved to 1 Spin-up device. Set and clear this bit by software. 01 RW RA2 SUD Writing the bit from 0 to 1 to issue COMRESET to the device Kept as`1'for normal operation Start switch of command list DMA engine. 00 RW 0 ST Writing the bit from 0 to 1 starts processing from PxCI bit 0. Writing the bit from 1 to 0 will clear PxCI register.
14 13 12:08 07:06 05
R R R R RW
0 0 0 0 0
FR ISS CCS
Different reset level is switched with bit5.
Reg_11CH (IO01+1Ch) : P0PRBS40B_PAT
User-defined pattern in PRBS check for internal test only.
Reg_120H (IO01+20h): P0TFD, Task file data of this port
The register copies specific fields of the task file when FISes are receive, like D2Hregister FIS PIO Setup FIS Set Device Bits FIS(not include BSY and DRQ bits) For MultiPM bit (Reg_174H bit 1)= 0 : The field is the received D2H Register FIS from all PM#0 to #15 devices, may be overlapped. 27
1/20/2009
XRS10L620 Rev 1.00
For MultiPM bit (Reg_174H bit 1)= 1 : The field is the received D2H Register FIS from only PM#0 device, no overlap with other PM#.
Bit(s) R/W default Symbol
31:16 15:08 R R 0h 0h ERR Reserved Task file error register
Description
Task file status register, with 3 bits that may affect AHCI 07:00 R 7Fh STS Bit7 : BSY Bit3 : DRQ Bit0 : ERR
Reg_124H (IO01+24h) : P0SIG, signature of this port
For MultiPM bit (Reg_174H bit 1)= 0 : The field is the received D2H Register FIS from all PM# devices, may be overlapped. For MultiPM bit (Reg_174H bit 1)= 1 : The field is the received D2H Register FIS from only PM#0 device, no overlap with other PM#.
Bit(s) R/W default Symbol
31:00 R FFFFFFFFh SIG
Description
Bit 31:24 : Cylinder high register (LBA [23:16]) Bit 23:16 : Cylinder low register (LBA [15:08]) Bit 15:08 : Sector number register (LBA [07:00]) Bit 07:00 : Sector count register
Reg_128H (IO01+28h) : P0SSTS (SCR0 : SStatus) Bit(s) R/W default Symbol
31:12 R 0 Reserved Indicates the current power state : 0h : Device not present or communication not established 1h : Active state 2h : Partial power management state 6h : Slumber power management state All other values reserved Indicates the negotiated speed : 0h : Device not present or communication not established 1h : Gen 1 rate negotiated 2h : Gen 2 rate negotiated All other values reserved Device detection and Phy state 0h : No device detected and Phy not ready 1h : Device presence detected but Phy not ready 3h : Device presence detected and Phy ready 4h : Phy in offline since bus disabled or bus in a BIST loopback mode All other values reserved
Description
11:08
R
0h
IPM
07:04
R
0h
SPD
03:00
R
0h
DET
Reg_12CH (IO01+2Ch) : P0SCTL (SCR2 : SControl)
28
1/20/2009
XRS10L620 Rev 1.00 Bit(s) R/W default Symbol
31:20 19:16 15:12 R R R 0h 0h 0h PMP SPM Reserved Port Multiplier Port: not used by AHCI Select power management, not used by AHCI Use PxCMD.ICC instead Indicates which power states are not allowed. 0h : No restrictions 1h : Disable transition to Partial state 2h : Disable transition to Slumber state 3h : Disable transition to both Partial and Slumber state All other values reserved Indicates the highest allowable speed : 0h : No speed restriction 1h : Limit speed negotiation to Gen 1 2h : Limit fastest speed negotiation to Gen 2 All other values reserved Control HBA's device detection and initialization. 0h : No action requested 1h : Perform initialization sequence like a hard reset. COMRESET is transmitted continuously until software change the field to 0h 4h : Disable the SATA interface and put Phy in offline mode All other values reserved This field may only be modified when PxXMD.ST is `0'.
Description
11:08
RW
0h
IPM
07:04
RW
0h
SPD
03:00
RW
0h
DET
Reg_130H (IO01+30h) : P0SERR Bit(s) R/W default Symbol
31:16 31:27 26 25 24 23 22 21 20 19 18 17 16 15:00 15:12 RWC R RWC RWC RWC RWC RWC RWC RWC RWC RWC RWC RWC RWC R 0000h 0h 0 0 0 0 0 0 0 0 0 0 0 0000h 0h X F T S H C D B W I N ERR DIAG
(SCR1 : SError) Description
Diagnostics Reserved Exchanged: 1=COMINIT(as Host) or COMRESET(as Device) received This bit is reflected in the P0IS.PCS bit Unknown FIS type received, include H2D and BIST FIS. Transport state transition error Link sequence error Handshake error: R_ERR received, result from CRC, disparity, or 8b/10b error CRC error Disparity error: not used by AHCI 10b to 8b decode error COMWAKE signal was detected by the Phy Phy internal error PhyRdy changed: This bit is reflected in P0IS.PRCS bit Error Reserved
29
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XRS10L620 Rev 1.00
11 10 9 8 7:2 1 0 RWC RWC RWC RWC R RWC RWC 0 0 0 0 0h 0 0 M I E P C T Internal error: Master or Target abort occurred in the PCI bus Protocol error: a violation of SATA protocol Persistent communication error Transient data integrity error: A data integrity error that was not recovered by the interface Reserved Recovered communication error: Communication was temporarily lost between host and device. Recovered data integrity error: A data integrity error occurred that was recovered by a retry operation.
Reg_134H (IO01+34h) : P0SACT (SCR3 : SActive) Bit(s) R/W default Symbol
31:00 RW1 0h DS
Description
Device status: used for FPDMA queuing operation prior to setting the PxCI.CI bit in the same command slot number. This field is clear via the Set Device Bits FIS, not by software.
Reg_138H (IO01+38h) : P0CI, Port0 command issue Bit(s) R/W default Symbol
31:00 RW1 0h CI
Description
Set by software and cleared by hardware. Indicate that a command has been built for a command slot number. Cleared when the HBA receives a FIS with BSY, DRQ, and ERR bits cleared.
Reg_13CH (IO01+3Ch) : P0NOTIF (SCR4) Bit(s) R/W default Symbol
Reserved 31:28 27:24 23:16 15:00 R RW R RWC 0h 0h 0h 0h CLRPMP CLRPMP The PM number for Reg_140H .CICLR to be cleared CLRPMP Reserved Bit indication of Port Multiplier #15 to #0 `1'=this PM# receive a SetDevBits FIS with the N bit set to 1. NOTIF The bit is cleared by SW writing `1', but not cleared due to a COMRESET
Description
Reg_140H (IO01+40h) : P0CICLR, Clear Port0 CI Bit(s) R/W default Symbol
30
Description
1/20/2009
XRS10L620 Rev 1.00
Force CI and SACT bits cleared by host Fill`1' to clear the respective CI/SACT bit, then the`1' will self-cleared to `0'. CICLR Only these CI bits belong to the same PM number can be cleared at a time. The PM# must be assigned at Reg_13FH bit[3:0] before this register is written
31:00
RW1
0h
Reg_144H (IO01+44h) : P0SDBFG Bit(s) R/W Default Symbol
31:00 RWC 0h SDBFG
Description
Set by the 32 Act bits of Set Device Bits FIS Cleared by software when writing `1' to each bit
Reg_148H to Reg_15FH (IO01+48h to 5Fh) : Registers for internal test.
Addr
Byte 3 Byte 2 Byte 1 8 7 6 5 Byte 0 4 3 2 1 fis_con_state FORCEPHYRDY GIO1_SEL[5:4] GIO0_SEL[5:4] PHYCTRLEN PRBS40BEN FORCE3G 0
Name
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 emptu_a2t empty_t2a
48h
Debug 0
0
err_queue
ff_a2t_err
ff_t2a_err
link_state
full_a2t
full_t2a
tp_state
crc_err
0
0
empty_t2a0
emptu_a2t0
4Ch
Debug 1
0
0
0
0
full_t2a0
0
0
0
PRBSALIGNLLEN
PRBS40BPATEN
PRBSALIGNEN
RXLOCKLLEN
PHYRDYCTRL
50h PHYCTRL
GIO3_SEL[5:4]
54h
PLLTEST
31
1/20/2009
GIO2_SEL[5:4]
PLLTESTSEL
BYPASSLD
LOCKDET
VFRSEL
Reserved
Reserved
INDSEL
PDPLL
PRBS40BLLEN
GIO3_SEL[3:0]
GIO2_SEL[3:0]
GIO1_SEL[3:0]
GIO0_SEL[3:0]
FORCE1.5G
PHYRSTI
Reserved
Reserved
Reserved
Reserved
XRS10L620 Rev 1.00
TXTSTPATSEL TXDRVLEVEL BYP_TXFIFO SLUMBER PLPBKEN SLPBKEN PARTIAL TXRATE PRBSEN Reserved Reserved Reserved reserved reserved reserved PDTX SQLCHENB PDRX
58h
TxTEST
PRBSALIGNOK / PRBSALIGNOKLL
PRBS40BOK / PRBS40BOKLL
RX_LOCK / RX_LOCKLL
CDR_CLKDP_DLY_EN
PRBSOK / PRBSOKLL
CDRCKOUT_SEL
BLK_3RDDN_EN
CMMDETLHEN
RCVK28_5DET
PRBSOKLLEN
CMMDETEN
BTALIGNEN
RXCRCBYP
PHFREEZE
SQTHSEL
CRCFHB
RXRATE
CRCFLB
Reserved
Reserved
UP2_EN
DCDEN
5Ch
RxTEST
Reg_148H (IO01+48h): P0Debug_0 Bit(s) R/W Default
31:00 R
Symbol
Debug_0 System Debug Port 0.
Description
Reg_14CH (IO01+4Ch): P0Debug_1 Bit(s) R/W Default
31:00 R
Symbol
Debug_1 System Debug Port 1.
Description
Reg_150H (IO01+50h): P0PHYCTRL Bit(s) R/W Default
31:28 RW 0000
Symbol
GIO3_SEL
Description
SEL[3:0], plus SEL[5:4] at Reg_154H bit [7:6], to select one of 64 sources to GIO3 pin output 08h : SIGLVD 09h : COMRSTINIT 0Ah : COMWAKE 0Bh : COMSAS 0Ch : PRBSOK 0Dh : RCVK28_5DET 0Eh : CDRCKOUT 0Fh : reserved
00h : reserved 01h : COM_DET0 02h : COM_DET1 SEL5,4= 03h : DTAVLD0 04h : DTAVLD1 0,0 05h : RX_ERR (FIFO over flow) 06h : RX_LOCK 07h : DTA_UNDFLW (FIFO under flow)
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EQ
PE
XRS10L620 Rev 1.00
00h : PRBS40BOK 08h : 0 01h : PRBSALIGN_OK 09h : 0 02h : 0 0Ah : 0 SEL5,4= 03h : TXRATE_DFT 0Bh : 0 04h : RXRATE_DFT 0Ch : 0 0,1 05h : DEADCK_DET_DFT 0Dh : 0 06h : INVALID_DFT(8b/10b error) 0Eh : 0 07h : RDERR_DFT (disparity error) 0Fh : 0 00h : 0 08h : SELOUT_DFT[0] 01h : XPOUT_DFT[1] 09h : SELOUT_DFT[1] 02h : XPOUT_DFT[2] 0Ah : SELOUT_DFT[2] SEL5,4= 03h : XPOUT_DFT[3] 0Bh : SELOUT_DFT[3] 04h : XPOUT_DFT[4] 0Ch : SELOUT_DFT[4] 1,0 05h : XPOUT_DFT[5] 0Dh : SELOUT_DFT[5] 06h : XPOUT_DFT[6] 0Eh : SELOUT_DFT[6] 07h : 0 0Fh : SELOUT_DFT[7] SEL5,4= 1,1 27:24 23:20 19:16 15 14 Reserved to 0 RW RW RW R RW 0000 0000 0000 0 RA8 FORCE1.5G GIO2_SEL GIO1_SEL SEL[3:0], plus SEL[5:4] at Reg_154H bit [5:4], to select one of 64 sources to GIO2 pin output SEL[3:0], plus SEL[5:4] at Reg_154H bit [3:2], to select one of 64 sources to GIO1 pin output Reserved Reserved. 0 = normal 1 = fixed at 1.5G mode, never changed to 3G during negotiation Reserved. when RX input signal > squelch threshold level and RX is locked, Reg_5CH bit 27 is high. Once the signal is going low, this bit is latched to low Reserved. PHYRSTI Set 1 to reset PHY, 0 to restore.
13:12 11
R RW
00 0 RXLOCKLL_EN
10 9 8 7
RW R RW RW
0 0 0 0
PHYRDY_CTRL
PRBSALIGNLLEN Transmit/check Align primitive with error latched to a low flag
6 5 4
RW RW RW
0 0 0
PRBSALIGNEN PRBS40BPATEN PRBS40BLLEN
Transmit/check Align primitive Transmit/check Dword pattern specified in Reg_1CH. Enable 40 bit PRBS or defined pattern transmit/check with error latched to a low flag
3 2
RW RW
0 0
PRBS40BEN FORCE3G
Enable 40 bit PRBS transmit/check 1=Fixed at 3G mode, never changed to 1.5G during speed negotiation
1
RW
0
FORCEPHYRDY 0: Normal operation. 1: Forced PHY ready regardless OOB power on initialization.
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0 RW 0 PHYCTRLEN Set 1 to control TXrate, RXrate, Slumber, Partial function
Reg_154H (IO01+54h): P0PLLTEST ** P1PLLTEST(IO01+D4h) is reserved, not available. Bit(s) R/W Default Symbol Description
Select different PLL test mode 000= Test mode disabled 100= Bandgap voltage 001= Vcoin voltage 101= Charge pump current source 010= Ground voltage 110= Charge pump current sink 011= Vddreg voltage 111= VCO free running Select Vcoin free running voltage 111 = 1.5V 011 = 1.0V 110 = 1.4V 010 = 0.9V 101 = 1.3V 001 = 0.7V 100 = 1.2V 000 = 0.5V 1 = Power down PLL 0 = Normal operation 1 = PLL is locked 0 = PLL is not locked
31:29
RW
000
PLLTESTSEL
28:26
RW
111
VFRSEL
25 24 23:21
RW R RW
0 1 000
PDPLL LOCKDET INDSEL
20
RW
0
BYPASSLD
19:08 7:6 5:4 3:2 1:0
R RW RW RW RW
0 0 0 0 0 GIO3_SEL GIO2_SEL GIO1_SEL
3 bits to select one of the signals below as `COM_DET0' name shown in Reg_50H bit [19:16] 000 = COMDET0/CMMDETLH0 100 = COMSAS 001 = PRBSOK/PRBSOKLL 101 =SQULCH 010 = COMINIT 110 = reserved 011 = COMWAKE 100 = reserved Bypass LOCKDET 1=POR_DG does not wait for LOCKDET (POR_DG=POR when BYPASSLD=1) 0=POR_DG waits for LOCKDET Reserved GIO3_SEL[5:4], see also Reg_150H bit[31:28] GIO2_SEL[5:4], see also Reg_150H bit[27:24] GIO1_SEL[5:4], see also Reg_150H bit[23:20] Reserved
Reg_158H (IO01+58h) : P0TxTEST **bit [15:6] of P1TxTEST (IO01+D8h) are reserved Bit(s) R/W Default
31 RW 0
Symbol
PARTIAL
Description
Power down TX and RX in Partial mode 1 = Power down 0 = No power down Read value is from SATA return value
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XRS10L620 Rev 1.00
30 29 28:24 23,22 RW RW R RW 0 1 0 RA9, 0 TXDRVLEVEL SLUMBER TXRATE Power down TX and RX in Slumber mode 1 = Power down 0 = No power down Read value is from SATA return value 1 = TX in 3G mode 0 = TX in 1.5G mode Read value is from SATA return value Reserved Select different TX driver levels 0,0= 500mV mode for Gen1i 0,1= 1000mV mode for proprietary use 1,0= 550mV mode for Gen1m 1,1= 1200mV mode for Gen1x Reserved Reserved BYP_TXFIFO Bypass TX FIFO 1 = Bypass Reserved 0 = No Bypass
21:18 17,16 15 14:12 11:08
R R RW R RW
0 00 0 0 0000 TXTSTPATSEL
7 6 5
R RW RW
0 0 0 PRBSEN PLPBKEN
Select different TX test patterns 0000=disabled 0001=IDLE 0100=High frequency pattern 0101=Low frequency pattern 0110=Mixed frequency pattern 0111=Alternate K28.3 pattern 1000=ALIGN 1001=COMINIT generation 1010=COMWAKE generation 1011=COMSAS generation Reserved Enable PRBS generation(TX) and checking(RX) 1 = Enable PRBS 0 = Disable PRBS Far-End Retimed Loopback 1 = TX/RX in Far-end loopback 0= TX/RX not in Far-end loopback Enable Near-End analog Loopback 1 = TX/RX in Near-End loopback 0= TX/RX not in Near-End loopback Control pre-emphasis level 000 = no pre-emphasis ... 111=strongest pre-emphasis 1 = Power down TX 0 = Not power down TX
4
RW
0
SLPBKEN
3:1
RW
000
PE
0
RW
0
PDTX
Reg_15CH (IO01+5Ch) : P0RxTEST **bit [21:8] of P1RxTEST (IO01+DCh) are reserved Bit(s) R/W Default
31 30 35 R R 1 0
Symbol
PRBSOK / PRBSOKLL CMMDETLH
Description
Switched by PRBSOKLLEN(bit15) 1 = PRBS OK 0 = PRBS error Comma detection latching high signal
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29 R 1 PRBS40BOK / PRBS40BOKLL Switched by PHYCTRL=>PRBS40BLL_EN(bit4) 1 = PRBS40B OK 0 = PRBS40B error Switched by PHYCTRL=>PRBSALIGNLL_EN(bit6) PRBSALIGNOK / PRBSALIGNOKLL 1 = PRBSALIGN OK 0 = PRBSALIGN error Switched by PHYCTRL=>RX_LOCKLL_EN(bit11) 1 = RX input signal > squelch threshold level and RX is RX_LOCK / locked RX_LOCKLL 0 = RX input signal < squelch threshold level or RX is not locked Reserved RXRATE UP2_EN 1 = RX in 3G mode 0 = RX in 1.5G mode Read value is from SATA return value Reserved
28
R
1
27
R
1
26 25 24 23 22
R RW RW RW RW
0 1 0 1 0
BLK_3RDDN_EN Reserved CDR_CLKDP_DLY Reserved _EN Select different CDRCKOUT clock frequency For Gen1 : CDRCKOUT_SEL 00=disabled 01=37.5MHz 10=75MHz 11=150MHz For Gen2 : 00=disabled 01=75MHz 10=150MHz 11=300MHz RX FIFO upper threshold CRCFHB 00= 12 01=13 10=14 11=15 RX FIFO lower threshold CRCFLB 00= 4 01=5 10=6 11=7 Select PRBSOK latching low enable PRBSOKLLEN 1 = Enable latching low for PRBSOK 0 = Disable latching low for PRBSOK Bypass RX Clock Rate Compensation FIFO RXCRCBYP 1 = Bypass 0 = No Bypass 1 = Enable comma detector in RX CMMDETEN 0 = Disable comma detector in RX Enable to select comma detection latching high CMMDETLHEN 1 = Enable comma detection latching high 0 = Disable comma detection latching high 1 = Enable byte alignment for comma detector BTALIGNEN 0 = Disable byte alignment for comma detector Control squelch threshold voltage levels 000 = normal 100 = +20 % SQTHSEL 001 = -10 % 101 = +40 % (for SAS) 010 = -20 % 110= reserved 011 = +10 % 111= reserved Reserved DCDEN PHFREEZE Dead(CDR Recovered) Clock Detection Enable 1 = Enable 0 = Disable Freeze phase selection of phase interpolator. 1 = Freeze phase 0 = Normal mode Control RX equalizer level 00 = no equalization ... 11 = strongest equalization
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21:20
RW
00
19:18 17:16 15 14 13 12 11
RW RW RW RW RW RW RW
01 01 0 0 1 0 1
10:8
RW
000
7:6 5 4
R RW RW
00 1 0
3:2
RW
11
EQ
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XRS10L620 Rev 1.00
1 0 RW RW 0 0 SQLCHENB PDRX Squelch circuit enable signal 0 = Enable squelch circuit 1 = Disable squelch circuit 1 = Power down RX lane 0 = Not power down RX lane
Reg_160H to Reg_16FH (IO01+60h to 6Fh) : Port 0 Task File registers for Port Multiplier #1 to #7
These fields are valid only when Reg_174H bit 1 ( P0MultiPM) is`1' for FIS-based switching
Reg_160H (IO01+60h) : PxTFD1 for PM# 1 Bit(s) R/W default Symbol
31:24 23:16 15:08 07:00 R R R R 0h 7Fh 0h 0h ERR1 STS1 ERRF STSF
Description
PortX, PM#1 Task file error register PortX, PM#1 Task file status register, with BSY, DRQ, ERR bits PortX, PM#F Task file error register PortX, PM#F Task file status register, with BSY, DRQ, ERR bits
Reg_164H (IO01+64h) : PxTFD23 for PM# 2,3 Bit(s) R/W default Symbol
31:24 23:16 15:08 07:00 R R R R 0h 7Fh 0h 7Fh ERR3 STS3 ERR2 STS2
Description
PortX, PM#3 Task file error register PortX, PM#3 Task file status register, with BSY, DRQ, ERR bits PortX, PM#2 Task file error register PortX, PM#2 Task file status register, with BSY, DRQ, ERR bits
Reg_168H (IO01+68h): PxTFD45 for PM# 4,5 Bit(s) R/W default Symbol
31:24 23:16 15:08 07:00 R R R R 0h 7Fh 0h 7Fh ERR5 STS5 ERR4 STS4
Description
PortX, PM#5 Task file error register PortX, PM#5 Task file status register, with BSY, DRQ, ERR bits PortX, PM#4 Task file error register PortX, PM#4 Task file status register, with BSY, DRQ, ERR bits
Reg_16CH (IO01+6Ch): PxTFD67 for PM# 6,7 Bit(s) R/W default Symbol
31:24 23:16 15:08 07:00 R R R R 0h 7Fh 0h 7Fh ERR7 STS7 ERR6 STS6
Description
PortX, PM#7 Task file error register PortX, PM#7 Task file status register, with BSY, DRQ, ERR bits PortX, PM#6 Task file error register PortX, PM#6 Task file status register, with BSY, DRQ, ERR bits
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XRS10L620 Rev 1.00 Reg_170H to Reg_17FH (IO01+70h to 7Fh) : Port 0 Additional Interrupt Status and Enable for PM # 1 to 7
These fields are valid only when Reg_174H bit 1 ( P0MultiPM) is`1' for FIS-based switching
Reg_170H (IO01+70h) : P0AIS, Port 0 Additional Interrupt Status Bit(s) R/W default Symbol
31:28 RWC 0h
Description
Bit 31: Reserved Bit 30: PM#7 DMA Setup FIS received interrupt flag Bit 29: PM#7 PIO Setup FIS received interrupt flag Bit 28: PM#7 D2H Register FIS received interrupt flag Bit 27: Reserved Bit 26: PM#6 DMA Setup FIS received interrupt flag Bit 25: PM#6 PIO Setup FIS received interrupt flag Bit 24: PM#6 D2H Register FIS received interrupt flag Bit 23: Reserved Bit 22: PM#5 DMA Setup FIS received interrupt flag Bit 21: PM#5 PIO Setup FIS received interrupt flag Bit 20: PM#5 D2H Register FIS received interrupt flag Bit 19: Reserved Bit 18: PM#4 DMA Setup FIS received interrupt flag Bit 17: PM#4 PIO Setup FIS received interrupt flag Bit 16: PM#4 D2H Register FIS received interrupt flag Bit 15: Reserved Bit 14: PM#3 DMA Setup FIS received interrupt flag Bit 13: PM#3 PIO Setup FIS received interrupt flag Bit 12: PM#3 D2H Register FIS received interrupt flag Bit 11: Reserved Bit 10: PM#2 DMA Setup FIS received interrupt flag Bit 09: PM#2 PIO Setup FIS received interrupt flag Bit 08: PM#2 D2H Register FIS received interrupt flag Bit 07: Reserved Bit 06: PM#1 DMA Setup FIS received interrupt flag Bit 05: PM#1 PIO Setup FIS received interrupt flag Bit 04: PM#1 D2H Register FIS received interrupt flag PM#F D2H Register FIS received interrupt flag Reserved
27:24
RWC
0h
23:20
RWC
0h
19:16
RWC
0h
15:12
RWC
0h
11:08
RWC
0h
07:04
RWC
0h
03 02:00
RW RW
0h 0h
Reg_174H (IO01+74h) : P0AIE, Port 0 Additional Interrupt Enable
Similar to P0IE, first layer enable is CFGM+4 bit 10 and GHC.IE bit
Bit(s) R/W default
31:28 RW 0h
Symbol
Description
Bit 31: reserved Bit 30: If set, INTA# issued when P0AIS bit 30=1 for PM#7 Bit 29: If set, INTA# issued when P0AIS bit 29=1 for PM#7 Bit 28: If set, INTA# issued when P0AIS bit 28=1 for PM#7
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27:24 RW 0h Bit 27: reserved Bit 26: If set, INTA# issued when P0AIS bit 26=1 for PM#6 Bit 25: If set, INTA# issued when P0AIS bit 25=1 for PM#6 Bit 24: If set, INTA# issued when P0AIS bit 24=1 for PM#6 Bit 23: reserved Bit 22: If set, INTA# issued when P0AIS bit 22=1 for PM#5 Bit 21: If set, INTA# issued when P0AIS bit 21=1 for PM#5 Bit 20: If set, INTA# issued when P0AIS bit 20=1 for PM#5 Bit 19: reserved Bit 18: If set, INTA# issued when P0AIS bit 18=1 for PM#4 Bit 17: If set, INTA# issued when P0AIS bit 17=1 for PM#4 Bit 16: If set, INTA# issued when P0AIS bit 16=1 for PM#4 Bit 15: reserved Bit 14: If set, INTA# issued when P0AIS bit 14=1 for PM#3 Bit 13: If set, INTA# issued when P0AIS bit 13=1 for PM#3 Bit 12: If set, INTA# issued when P0AIS bit 12=1 for PM#3 Bit 11: reserved Bit 10: If set, INTA# issued when P0AIS bit 10=1 for PM#2 Bit 09: If set, INTA# issued when P0AIS bit 09=1 for PM#2 Bit 08: If set, INTA# issued when P0AIS bit 08=1 for PM#2 Bit 07: reserved Bit 06: If set, INTA# issued when P0AIS bit 06=1 for PM#1 Bit 05: If set, INTA# issued when P0AIS bit 05=1 for PM#1 Bit 04: If set, INTA# issued when P0AIS bit 04=1 for PM#1 If set, INTA# issued when P0AIS bit 03=1 for PM#F `1' will always receive D2H FIS independent of BSY, DRQ bit PassD2H value MultiPM NCQSW Enable multiple PM devices FIS-based switching, for PM#0 to 7 and #F only. It should be disabled for other PM#, the PM#8 to #E. Enable NCQ
23:20
RW
0h
19:16
RW
0h
15:12
RW
0h
11:08
RW
0h
07:04
RW
0h
03 02 01 00
RW RW RW RW
0 0 0 0
Reg_178H (IO01+78h) : P0AUFS, additional unknown FIS interrupt status & enable Bit(s) R/W default Symbol
Do not use 31 30:29 28:24 23 RWC R RW R 0h 0h 0h 0 Reserved Do not use Reserved
Description
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FIFO threshold to request PCI write memory from SATA0 000 = 7/8 FIFO full 001 = 6/8 FIFO full 010 = 5/8 FIFO full 011 = 4/8 FIFO full 100 = 3/8 FIFO full 101 = 2/8 FIFO full 110 = 1/8 FIFO full 111 = 1/8 FIFO full =1 when main FIFO is non-empty FIFO threshold to request PCI read memory to SATA0 000 = 7/8 FIFO empty 001 = 6/8 FIFO empty 010 = 5/8 FIFO empty 011 = 4/8 FIFO empty 100 = 3/8 FIFO empty 101 = 2/8 FIFO empty 110 = 1/8 FIFO empty 111 = 1/8 FIFO empty Bit 15: enable PM#7 Unknown FIS received interrupt Bit 14: enable PM#6 Unknown FIS received interrupt Bit 13: enable PM#5 Unknown FIS received interrupt Bit 12: enable PM#4 Unknown FIS received interrupt Bit 11: enable PM#3 Unknown FIS received interrupt Bit 10: enable PM#2 Unknown FIS received interrupt Bit 09: enable PM#1 Unknown FIS received interrupt Bit 08: reserved Bit 07: PM#7 Unknown FIS received interrupt flag Bit 06: PM#6 Unknown FIS received interrupt flag Bit 05: PM#5 Unknown FIS received interrupt flag Bit 04: PM#4 Unknown FIS received interrupt flag Bit 03: PM#3 Unknown FIS received interrupt flag Bit 02: PM#2 Unknown FIS received interrupt flag Bit 01: PM#1 Unknown FIS received interrupt flag Bit 00: reserved
22:20
RW
0
19
R
0
18:16
RW
0
15:08
RW
0h
07:00
RWC
0h
Reg_17CH to Reg_17FH (IO01+7Ch to 7Fh) : Reserved.
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Each Port Multiplier has 80h memory space. The XRS10L620 support 8 PM numbers, PM#0 to PM#7, at the same time with
XRS10L620 Register Mapping
00h
1KB align
System Memory Space Mapping
128B align
PMP TCB PWA CFL reserved reserved Command Table Base Address (Low) Command Table Base Address (High)
(IOG+00h to 7Fh)
10h
CH 0
00h
00h H2D Command FIS 40h 60h 80h ATAPI Packet Reserved
Data Base Address(Low) PRD0 Data Base Address (High) Reserved
EOT
Fig 6.1 XRS10L620 register and system memory mapping
General AHCI Control Registers 20h 80h
CH 1 CH 2
(IOG+80h to FFh)
send IDE, GIO,Test Registers 3E0h 100h (IO01+00h to 7Fh) P0FB P0CLB Receive
CH 31 256B align
PRD1
A0h
PRD2
B0h 00h 20h 40h 58h 60h 80h 100h
PM#1
DMA setup FIS PIO setup FIS PM#0 or All D2H Register FIS Set Device Bits FIS Unknown FIS
PRDN
SATA0 Registers
Command Table
180h (IO01+80h to FFh)
P1CLB P1FB
PM#2
400h 1FFh
PM#7 PM#F
switching.
SATA1 Registers
380h
7.1 Received FIS structure
data N
The Unknown FIS include the H2D FIS and BIST FIS.
90h
Byte Count
data 1 data 2
7. System Memory Structure
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40h
data 0
FIS-base switching. Higher Port Multiplier numbers like PM#8 to PM#14, can be connected also under Command-base
XRS10L620 Rev 1.00
The structure is in the system memory and pointed in unit of 256 bytes by PxFB, as shown in Fig. 6.1.
XRS10L620 Rev 1.00 7.2 Command List Structure
Total 32 Command Headers are defined with 4-DW(16 bytes) each that details the direction, type, and scatter/gather pointer of the command. The Command List is aligned in 1024 bytes. Further details of each field are listed below. DW# Bit# 31:16 Reserved 15:12 Port Multiplier Port(PMP): Indicates the port number that should be used when constructing data FISes on transmit, and to check against all FISes received for this command. 11 Data phase flag. Description
10 Clear Busy upon R_OK(C): When set, the HBA shall clear PxTFD.STS.BSY and PxCI bit after transmitting this FIS and receive R_OK, no need to wait the relative D2H FIS. Host DW0 mode : Set to one for first H2D FIS of soft reset sequence
09 BIST(B): reserved 08 Reserved 07 Prefetchable(P): When set, the HBA will prefetch 8 more PRDs during Data FIS transfer. The bit is not available if NCQSW or MultiPM bits are enabled(PxAIE bit1,0) 06 Write(W): When set, the direction is device write (data from system memory to device) 05 ATAPI(A): When set, indicates a PIO setup FIS shall be sent by the device indicating a transfer for the ATAPI packet. 04:00 Command FIS Length(CFL): Length of the Command FIS, in DW.
DW1 31:00 Reserved 31:07 Command Table Base Address(Low):low 32 bits physical address pointer to the command DW2 table that is 128-byte aligned 06:00 Reserved DW3 31:07 Command Table Base Address(High):high 32 bits physical address pointer. 06:00 Reserved
7.3 Command Table and PRD table
The table contains the command FIS, ATAPI Command, and PRD table as shown in Fig6.1. It is aligned in 128 bytes. The Command FIS field contains the H2D FIS to be sent to the device. The DWord count is same as CFL field in Command Header. The ATAPI Packet field contains either 12 or 16 bytes to transmit if `A' bit is set in the Command Header. 42
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The PRD table format is as below : DW# Bit# DW0 31:00 Data Base Address(Low) DW1 31:00 Data Base Address(High) DW2 31:00 Reserved 31 End of Transfer(EOT): indicates the last PRD of the whole list DW3 30:17 Reserved 16:00 Byte count of this PRD, 64KB(10000h) maximum Description
8. PCB High-Speed Layout Design Guidelines
1. 2. 3. High speed differential signals (TX+ & TX-, RX+ & RX-) should be routed as micro-strips on layer 1. No via or stubs for these critical traces. Differential pairs trace length should be identical. Impedance should be controlled at 100 ohms +- 5% for differential pair, and 50 ohms +- 10% for single ended. Keep the trace length of differential pairs as short as possible. Avoid sharp turns, use rounded corner. It is highly recommended to keep them within two inches long. Make sure no other signals are routed near these critical traces. Keep a good separation between these differential pairs and other signals, minimum of 50 mils clearance is recommended. 4. Recommended board stack-up and routing example: Material: FR4, with Dielectric constant of 4.2, and total thickness 62 mils. Thickness Layer 1, Signal FR4 Prepreg Layer 2, Ground FR4 Prepreg Layer 3, Power FR4 Prepreg Layer 4, Signal 5. 6. 7. 0.5 oz 4 mils 1 oz 47 mils 1 oz 4 mils 0.5 oz Diff Pair Width 8 mils Diff Pair Spacing 12 mils
When the differential layout cannot be achieved, e.g. around the connector area, neck-down technique to maintain single-ended 50 ohms is highly recommended. For other signals where VIA is unavoidable, anti-pad is required to provide adequate clearance. Place AC coupled 10nF capacitors as close as possible to the connector end, minimize the soldering pad area. The layout of capacitors can be combined with SATA connector to minimize impedance discontinuities. Use smaller footprint like 0402 to minimize package parasitic.
8. 43
Use surface mount SATA connector, avoid over-soldering. Minimize the width of RX and TX soldering pads for SATA
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XRS10L620 Rev 1.00
connector. 9. Separate analog power island on top layer for VDDA1,VDDA2,VDDA3, etc... via used to connect to the ferrite bead should be placed close to device power pins. 10. It is recommended that Analog power supplies VDDA should be isolated from the core VDD1.8V power plane through a noise suppression ferrite bead, which should provide 30dB or more attenuation for frequency less than 650 MHz. 11. Put decoupling capacitors with value of both 0.1uF and 0.01uF after ferrite bead. Place all decoupling capacitors as close to the device pins as possible. 12. A Ground plane should be on layer 2, the Ground plane should be solid underneath the high speed differential pairs to provide good return path. 13. Put enough Ground stitches throughout the board. 14. Each digital ground pin (GND) must have solid connection with PCB GND plane by at least 2 vias or other traces with it. 15. Signals should avoid crossing the split power planes. If have to, add some bypass capacitors across the split planes. For example, if some signals across 1.8V and 3.3V planes on the adjacent layer, then put a 0.1uF capacitor connecting 1.8V and 3.3V near the signals.
9. Electrical Characteristics
Specifications are for Commercial Temperature range, 0C to +70C, unless otherwise specified.
9.1 Absolute Maximum Ratings Symbol Parameter
VDD33 VDD18 VDDA Vin Tstg HBM MM I/O Supply Voltage Core Supply Voltage Analog Supply Voltage Input Voltage Storage Temperature ESD capability - HBM ESD capability - MM
Ratings
3.7 1.98 1.98 -0.3 ~ VDD33+0.3 -55 ~ 125 2000 200
Unit
V V V V C V V
9.2 Typical Operating Condition Parameter Min. Typ. Max. Unit Operating Temperature
Digital IO (VDD33) Digital Core (VDD18) SATA PHY (VDDA) -10 3.14 1.75 1.75 3.3 1.8 1.8 70 3.63 1.98 1.98 C V V V
Note
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XRS10L620 Rev 1.00 9.3 DC Specifications Parameter
SATA1.5G Digital IO (IDD33) SATA3G SATA1.5G SATA3G SATA1.5G SATA PHY (IDDA) SATA3G Input low voltage (Vil) Input high voltage (Vih) Output low voltage (Vol) Output high voltage (Voh) Weak pull high resistance 2.4 39 47 116 2.0 0.4 125 140 142 0.9 7.6 118 118 125 55 170 220 125 60 190 245 126 mA
Min. Typ. Max. Unit
4.6 55 60 mA Min.=idle
Note
Typ.=Read/Write at PCI 66MHz Max.=Read/Write at PCIX 100MHz (SATA 3G is for internal test only.)
Digital Core (IDD18)
mA Condition as IDD33. mA (SATA 3G is for internal test only.) mA Condition as IDD33. All VDDA1,2,3,4 current. mA (SATA 3G is for internal test only.) V V V V K Io= 8mA Io= -8mA
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10. Package Dimension
Top View D1=20mm
e = 0.5mm b = 0.2mm c =0.15mm L1=1.0m m
Exar
XRS10L620
E1=14mm
Side View A2=1.4mm A1=0.1mm
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11. Appendix
11.1Product ordering information 11.1.1 IC Marking Information XRS10L620 LQFP 128 pin TBD
11.1.2 Product Ordering Information
X
R
S
1
0
L
6
2
0
C
V
F
Valid Combinations XRS10L620 CV-F
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1/20/2009
XRS10L620 Rev 1.00
11.2 Soldering temperature profile (a) Temp. inc gradientAvg. 1~4/sec. (b) Preliminary heatingTemp.150~200/sec., 70~150/sec. (c) Temp. inc. gradientAvg. 1~3/sec. (d) Actual heatingTemp. 260 max 250 up 20sec max (e) Temp.220 up 40~70sec. (f) CoolingNatural Cooling or Forced Cooling
*Package Surface Temp.
260 250 220
150~200
RT (a)
(b)
(c)
(d)
(f)
(e)
48
1/20/2009

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